? semiconductor components industries, llc, 2002 april, 2002 rev. 0 1 publication order number: and8085/d and8085/d an introduction to fst prepared by fred zlotnick on semiconductor fast switch technology (fst) was introduced into the marketplace in the early nineties and has become quite popular with the networking and computing design community to solve many specialized problems. will booth of insight onsite ? claims the market was nearly $200 m in the year 2000, and expected to continue to grow over the next ten years. fst is the dominant bus switch technology, prevailing over the less popular cbt (cross bar technology). fst is manufactured by on semiconductor and several other important suppliers. fst is very simply logic reduced to switches. several 3state devices and buffers/multiplexers are constructed using nchannel switches instead of logic. the result is the same logic function, with nearly zero delay. although, this sounds perfect, the fst device has no drive capabilities of its own, but merely passes a signal along, more or less unimpeded. 2.2 v 2.2 v 0 0 +5 v figure 1. for those of you who want to understand the why and how of this family, this diagram shows a single nchannel fet switch, biased at +5.0 v at the gate. a signal will pass through the device, or not, depending upon the bias of the gate. interestingly, the fet can conduct in either direction and unlike a logic gate the time it takes for a signal to pass through this gate is close to zero. another interesting property is this fet, which acts just like a 5.0 v switch, until the voltage reaches close to the supply voltage (vcc). if the voltage on the left were to reach 4.3 volts, the output will be limited to within one v f of supply or approximately 4.3 volts. this would at first seem to be a stumbling block, however, remember that many 5.0 volt circuits are attlo compatible and any voltage > 2.2 volts is redundant. for acmoso compatible circuits, the input must exceed 3.5 volts, so 4.3 v is not much of a problem. in fact, this phenomenon, called `body effect' can be used to your advantage. if the fst has a vccv f as its supply, by inserting a diode in series with its supply, then, the drop will be 1.5 v. if one side of the fet were connected to a ttl compatible, 5.0 v device and the other were connected to a standard cmos device operating at 3.3 v, then the fst device would limit the voltage seen by the cmos device, but the 3.3 v output would flow unimpeded to the ttl device. this then becomes a nearly perfect logic level translator, with almost zero delay (when turned on). +3.5 v +5 v 0 0 +5 v figure 2. +5 v +v cc application note http://onsemi.com
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